| 摘要 |
Latency requirements for Ethernet link partners comprising PHY devices and memory buffers, may be determined for packets pending transmission. Transmission may be interrupted for a first packet having greater latency than a second packet, and the second packet may be transmitted. The second packet may be interrupted for transmission of a third or more packets. Packets are inspected for marks and/or for OSI layer 2 or higher OSI layer information to determine the latency requirements prior to completion of transmission of the first packet. The second packet is transmitted after a first portion of the first packet and/or prior to a second portion. Delimiters are inserted among the first and/or second packets for interrupting transmission. A PHY layer, MAC layer and/or higher OSI layer of the second link partner may receive, buffer and/or parse the packets and/or packet portions and/or may reconstruct the first packet and/or the second packet.
|
