发明名称 BUS ENHANCED NETWORK ON CHIP
摘要 A system that includes multiple modules of an integrated circuit; a network on chip that is coupled to the multiple modules; a bus, coupled in parallel to the network on chip to the multiple modules; wherein a latency of the bus is lower and more predictable than an average latency of the network of chip.
申请公布号 US2011022754(A1) 申请公布日期 2011.01.27
申请号 US20080745711 申请日期 2008.12.07
申请人 TECHNION RESEARCH & DEVELOPMENT FOUNDATION LTD 发明人 CIDON ISRAEL;KOLODNY AVINOAM;ISASK'HAR WALTER ZIGMOND
分类号 G06F13/00 主分类号 G06F13/00
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