METHOD FOR REDUCING TUNNEL REGION OF EEPROM

摘要

PURPOSE: A method for reducing tunnel region of EEPROM is provided to reduce a size of a memory device and maximize a storing capacitance by surmounting a reducing limit of a tunnel region by a lithography technique and obtaining a greatly decreased tunnel region. CONSTITUTION: A drain region(1) is formed on a semiconductor substrate. An oxidation film (3) grow to the drain region(1). A photosensitivity film(5) is covered on the oxidation film(3) according to a general lithography technique. An ion implantation is performed on the photosensitivity film(5). A reducing rate is decreased because an inclination angle of the ion implantation is decreased and a circular width of a damage circle(9) is decreased. A greatly small tunnel region is obtained because inclination angle of the ion implantation is increased and the circular width of the damage circle(9) is increased.