发明名称 ESD ANALYSIS DEVICE AND ESD ANALYSIS PROGRAM USED FOR DESIGNING SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING SEMICONDUCTOR DEVICE
摘要 An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.
申请公布号 US2011022376(A1) 申请公布日期 2011.01.27
申请号 US20100874782 申请日期 2010.09.02
申请人 NEC ELECTRONICS CORPORATION 发明人 KOBAYASHI SUSUMU;HIRATA MORIHISA;OKUSHIMA MOTOTSUGU;KITAYAMA TOMOHIRO;KATOU TETSUYA
分类号 G06F17/50 主分类号 G06F17/50
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