发明名称 TSVS Having Chemically Exposed TSV Tips for Integrated Circuit Devices
摘要 A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.
申请公布号 US2011018107(A1) 申请公布日期 2011.01.27
申请号 US20100899754 申请日期 2010.10.07
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 BONIFIELD THOMAS D.;GOODLIN BRIAN E.;EISSA MONA M.
分类号 H01L23/48 主分类号 H01L23/48
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