发明名称 Electrical via with lateral extensions
摘要 <p>The via (23) has conductive outgrowths (27) integral with the via extending in pores of a porous region (25) of a semiconductor substrate (W1). The porous region extends from a portion of the periphery of the via. A thin layer (29) is made of a thermally conductive and electrically-insulating material, and insulates the via from the substrate. The porous region extends across a width ranging between 5 and 20 percentages of the diameter of the via. An independent claim is also included for a method for manufacturing an electrical connection via connecting a front surface of a substrate to a rear surface of the substrate.</p>
申请公布号 EP2278614(A1) 申请公布日期 2011.01.26
申请号 EP20100166937 申请日期 2010.06.22
申请人 STMICROELECTRONICS (CROLLES 2) SAS 发明人 CHAABOUNI, HAMED;CADIX, LIONEL
分类号 H01L21/768;H01L23/48;H01L25/065 主分类号 H01L21/768
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