| 摘要 |
Techniques for achieving linear operation for a phase frequency detector and a charge pump in a phase-locked loop (PLL) are described. The phase frequency detector receives a reference signal and a clock signal, generates first and second signals based on the reference and clock signals, and resets the first and second signals based on only the first signal. The first and second signals may be up and down signals, respectively, or may be down and up signals, respectively. The phase frequency detector may delay the first signal by a predetermined amount, generate a reset signal based on the delayed first signal and the second signal, and reset the first and second signals with the reset signal. The charge pump receives the first and second signals and generates an output signal indicative of phase error between the reference and clock signals.
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