| 摘要 |
A pulse shaper comprises two reversible binary counters, each of which has synchronization pulse input, input for add-subtract mode set, synchronous load enable input, inputs for loading data supplying, compute mode enable input, input for asynchronous setting to zero position, overloading output, inverter 3, two-input element OR, a circuit comprising in series connected resistor and capacitor, a start/stop device comprising a synchronous D-trigger with input of asynchronous set to zero position, first and second AND elements, three-input element OR. Third two-input element OR is incorporated. |
