| 摘要 |
A data processing system comprising a memory array having a plurality of memory cells and read circuitry for reading a logic value stored in one of the plurality of memory cells. The read circuitry is operable perform two substantially simultaneous reads of the stored logic value. A voltage controller is provided and is operable to selectively vary a level of a supply voltage to the memory array. Detection circuitry is provided for detecting, in dependence upon the two substantially simultaneous reads, when the supply voltage level causes the read result to be unreliable.
|
