发明名称 Processing apparatus for storing branch history information in predecode instruction cache
摘要 The present invention provides an information processing apparatus having a predecoder decoding an operation code in an input instruction, generating conditional branch instruction information indicating that the input instruction is a conditional branch instruction and instruction type information indicating a type of the conditional branch instruction when the input instruction is a conditional branch instruction, and writing the input instruction, from which the operation code is deleted, the conditional branch instruction information and the instruction type information to the instruction cache memory, and a history information writing unit writing history information indicating whether or not the conditional branch instruction was branched, as a result of executing the conditional branch instruction stored in the instruction cache memory, to an area in the instruction cache memory, where the operation code of the conditional branch instruction is deleted.
申请公布号 US7877578(B2) 申请公布日期 2011.01.25
申请号 US20080071586 申请日期 2008.02.22
申请人 FUJITSU SEMICONDUCTOR LIMITED 发明人 YAMAZAKI YASUHIRO
分类号 G06F9/30;G06F9/40;G06F15/00 主分类号 G06F9/30
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