发明名称 DISPLAY
摘要 PROBLEM TO BE SOLVED: To reduce a circuit scale of a decoder circuit outputting a voltage corresponding to an 8-bit digital value.SOLUTION: The decoder circuit 528f outputs a voltage corresponding to a digital value based on a 8-bit digital value and includes: a first decoder circuit 532b and a second decoder circuit 534b which output one voltage respectively using upper-order 6 bits of the 8-bit digital value; a selection circuit 536b which receives voltages output from the first decoder circuit 532b and the second decoder circuit 534b, and distributes the two voltages to three input terminals; and an intermediate voltage output circuit 557 which outputs an intermediate voltage which is one of five intermediate voltages based on the three voltages selected by the selection circuit. The first decoder circuit 532b and the second decoder circuit 534b respectively include a select-switch-type decoder circuit 542 and a tournament-type decoder circuit 544.
申请公布号 JP2011013335(A) 申请公布日期 2011.01.20
申请号 JP20090155719 申请日期 2009.06.30
申请人 HITACHI DISPLAYS LTD 发明人 AKIYAMA KENICHI;KOTANI YOSHIHIRO;SEHATA HIROKO;KODERA KOICHI
分类号 G09G3/36;G02F1/133;G09G3/20 主分类号 G09G3/36
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