发明名称 |
GENERATION METHOD OF SCAN CHAIN, GENERATION PROGRAM OF THE SCAN CHAIN, AND INTEGRATED CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To generate a scan chain so that tests between a plurality of domains obtained by dividing one circuit are performed, relative to the test of an integrated circuit.SOLUTION: If a power consumption when operating a scan shift including a plurality of flip-flops exceeds an allowable value during the test of the integrated circuit, the plurality of flip-flops included in the scan chain are divided into a plurality of groups. In dividing, partial flip-flops in the plurality of flip-flops are included in a plurality of groups based on a transmission route of a signal when the integrated circuit is operated actually. The flip-flops included in the plurality of groups are connected to each scan chain generated in each of the plurality of groups. |
申请公布号 |
JP2011013159(A) |
申请公布日期 |
2011.01.20 |
申请号 |
JP20090159208 |
申请日期 |
2009.07.03 |
申请人 |
FUJITSU SEMICONDUCTOR LTD |
发明人 |
IKENISHI JO;YABUMOTO TOMOKO |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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