发明名称 METHOD OF MANUFACTURING ELECTRONIC PARTS PACKAGING STRUCTURE
摘要 PROBLEM TO BE SOLVED: To provide a method of manufacturing an electronic part packaging structure by using a circuit board in which an electrolytic plating layer can be formed on a connection pad, without the occurrence of failures, even when the number of connection pads on the circuit board increases and the pitch is narrowed.SOLUTION: The method includes a step of forming an n-layered (n is an integer of 1 or more) wiring layers electrically connected to a metal plate 10 by stacking wiring layers 38, 38a, 38b and insulation layers 20, 20a on the metal plate 10; a step of forming an electrolytic plating layer 44 on a connection pad portion of the uppermost wiring layer 38b of the n-layered wiring layer by electrolytic plating using the metal plate 10 and the wiring layers 38, 38a, 38b as a plating power-supply path; a step of packaging an electronic part 30 electrically connected to the electrolytic plating layer 44 disposed on the uppermost wiring layer 38b; and a step of removing the metal plate 10 over its entirety to expose the under surface of the lowermost wiring layer 38 of the n-layered wiring layer.
申请公布号 JP2011014944(A) 申请公布日期 2011.01.20
申请号 JP20100236793 申请日期 2010.10.21
申请人 SHINKO ELECTRIC IND CO LTD 发明人 NAKAMURA JUNICHI;SAKAGUCHI TETSUO;MUKOYAMA KAZUYA;ODA SACHIKO;YUMOTO MASAHIRO
分类号 H01L23/12 主分类号 H01L23/12
代理机构 代理人
主权项
地址