| 摘要 |
PROBLEM TO BE SOLVED: To provide an analog/digital (A/D) converter that achieves wideband and high-speed sampling rate while fixing an input analog voltage range.SOLUTION: Each of voltage controlled delay generator cells VCDG_0 to 3 outputs, as a stop pulse signal "stop", a result of comparing an input analog voltage with a ramp voltage generated by a capacitor with a current supplied from a plurality of (e.g., four) constant current sources via a current switch. The voltage controlled delay generator cells VCDG_0 to 3 are disposed in parallel as many as the number of the constant current sources. After discharging ramp voltage under control of a control circuit CTL, first of all, the different number of current switches are turned on by the VCDG_0 to 3, and further, all current switches of the VCDG_0 to 3 are turned on when a start pulse signal "start" rises, thereby generating the ramp voltage in each of capacitors. Output delay times of stop pulse signals "stop" 0 to "stop" 3 of the VCDG_0 to 3 are converted into digital data by temporal digital converter TDC_0 to 3 and converted into a predetermined code by an encoder ENC. |
