发明名称 MECHANISM FOR CLOCK SYNCHRONIZATION
摘要 A method and apparatus for synchronizing time between a master device and a target device arranged across a network, wherein the target device communicates to the master device through a PCIe interconnect includes transmitting a first message at a first time from the master device to the target device, the first message including a message indicator; and receiving a reply message at a subsequent time from the target device to the master device, the reply message including the message indicator.
申请公布号 WO2011008327(A1) 申请公布日期 2011.01.20
申请号 WO2010US34350 申请日期 2010.05.11
申请人 INTEL CORPORATION;STANTON, KEVIN;HARRIMAN, DAVID, J. 发明人 STANTON, KEVIN;HARRIMAN, DAVID, J.
分类号 H04L7/10 主分类号 H04L7/10
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