发明名称 |
Integrated circuit with control circuit for performing retention test |
摘要 |
An integrated circuit includes an array of memory cells, a clock generator configured to generate a clock signal, and a control circuit configured to perform a retention test on the array of memory cells based on the clock signal. A period of the clock signal defines a retention period for the retention test.
|
申请公布号 |
US7872931(B2) |
申请公布日期 |
2011.01.18 |
申请号 |
US20080251010 |
申请日期 |
2008.10.14 |
申请人 |
QIMONDA NORTH AMERICA CORP. |
发明人 |
FEKIH-ROMDHANE KHALED |
分类号 |
G11C7/00;G11C8/00;G11C29/00 |
主分类号 |
G11C7/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|