发明名称 |
Memory addressing scheme using partition strides |
摘要 |
Systems and methods for addressing memory where data is interleaved across different banks using different interleaving granularities improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected to modify the number of sequential addresses mapped to each DRAM and change the interleaving granularity. A memory addressing scheme is used to allow different partition strides for each virtual memory page without causing memory aliasing problems in which physical memory locations in one virtual memory page are also mapped to another virtual memory page. When a physical memory address lies within a virtual memory page crossing region, the smallest partition stride is used to access the physical memory.
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申请公布号 |
US7872657(B1) |
申请公布日期 |
2011.01.18 |
申请号 |
US20060454362 |
申请日期 |
2006.06.16 |
申请人 |
NVIDIA CORPORATION |
发明人 |
EDMONDSON JOHN H.;VAN DYKE JAMES M. |
分类号 |
G06F12/02;G06F13/00;G06F13/28;G09G5/399 |
主分类号 |
G06F12/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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