发明名称 Manufacturing method for semiconductor integrated circuit device
摘要 In mass production of CMIS integrated circuit devices or the like, electric characteristics, such as Vth (threshold voltage) or the like, disadvantageously vary due to variations in gate length of the MISFET. This problem has become serious because of a short channel effect. In order to solve the problem, various kinds of feed-forward techniques have been studied in which a subsequent variation factor process is regulated to be reversed with respect to variations in a previous variation factor process so as to cause these variation factors to cancel each other out. Since the feed-back technique has an effect of the cancellation process over the entire system, the technique can be relatively easily applied to a product with a single type of MISFE, but is difficult to be applied to a product equipped with a plurality of types of MISFETs. The invention is adapted to adjust the amount of halo implantation by multivariate analysis based on the result of a patterning step of the gate electrode and a film forming step of an offset spacer.
申请公布号 US7871871(B2) 申请公布日期 2011.01.18
申请号 US20090393087 申请日期 2009.02.26
申请人 RENESAS ELECTRONICS CORPORATION 发明人 HISHIKI MASANOBU;MIURA YAICHIRO;KAWASHIMA HIROSHI;MITSUDA KATSUHIRO
分类号 H01L21/66 主分类号 H01L21/66
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