CLOCK AND DATA RECOVERY CIRCUIT AND SYSTEM USING THE SAME

摘要

A clock and data recovery circuit may include a phase detection unit, a first filtering unit, a second filtering unit, and a phase interpolation unit. The phase detection unit compares a clock signal with data and generates a plurality of early phase detection signals and a plurality of late phase detection signals. The first filtering unit generates an early enable signal and a late enable signal based on the number of early phase detection signals and the number of late phase detection signals that have been generated. The second filtering unit generates an up signal and a down signal based on a difference between the number of times that the early enable signal has been generated and the number of times that the late enable signal has been generated. The phase interpolation unit controls the phase of the clock signal according to the up signal and the down signal.

主权项

1. A clock and data recovery circuit, comprising:
a phase detection unit configured to compare a clock signal with data and generate a plurality of early phase detection signals and a plurality of late phase detection signals; a first filtering unit configured to generate an early enable signal and a late enable signal based on a number of the plurality of early phase detection signals and a number of the plurality of late phase detection signals that have been generated; a second filtering unit configured to generate an up signal and a down signal based on a difference between a number of times that the early enable signal has been generated and a number of times that the late enable signal has been generated; and a phase interpolation unit configured to control a phase of the clock signal according to the up signal and the down signal.