NEGATIVE CAPACITANCE LOGIC DEVICE, CLOCK GENERATOR INCLUDING THE SAME AND METHOD OF OPERATING CLOCK GENERATOR

摘要

A negative capacitance logic device includes a first field effect transistor (FET) and a second FET. The first FET is coupled between a power supply voltage and an output node, and the first FET includes a ferroelectric having a negative capacitance. The second FET is coupled between the output node and a ground voltage, and the second FET includes a ferroelectric having a negative capacitance. The negative capacitance logic differentiates an input voltage applied to an input node to provide an output voltage at the output node.

主权项

1. A negative capacitance logic device comprising:
a first field effect transistor (FET) coupled between a power supply voltage and an output node, the first FET including a ferroelectric having a negative capacitance; and a second (FET) coupled between the output node and a ground voltage, the second FET including a ferroelectric having a negative capacitance, wherein the negative capacitance logic is configured to differentiate an input voltage applied to an input node to provide an output voltage at the output node, wherein the first FET includes a p-channel FET that has a source region coupled to the power supply voltage, a gate electrode coupled to the input node and a drain region coupled to the output node, wherein the second FET includes an n-channel FET that has a drain region coupled to the power supply voltage, a gate electrode coupled to the input node and a source region coupled to the output node, wherein each of the first FET and the second FET includes a dielectric layer including at least the ferroelectric, wherein the dielectric layer is formed between the gate electrode and an channel region that is formed between the drain region and the source region in a substrate, and wherein the dielectric layer further comprises a gate oxide layer and a metal layer which are sequentially interposed between the channel region and the ferroelectric.