发明名称 |
PHASE-LOCKED LOOP CIRCUIT AND COMMUNICATION APPARATUS |
摘要 |
A PLL circuit of which low power consumption and miniaturization are satisfied at the same time is provided. A phase comparator of the PLL circuit includes a counter and a time-to-digital converter. The counter receives a reference clock signal and a low frequency clock signal obtained by dividing an output of a digital controlled oscillator, and a high frequency clock signal. The counter detects a phase difference between the reference clock signal and the low frequency clock signal by counting the clock number of the high frequency clock signal. The time-to-digital converter receives the reference clock signal and the low frequency clock signal. The time-to-digital converter detects the phase difference between the reference clock signal and the low frequency clock signal to the accuracy of a time period shorter than a cycle of the high frequency clock signal, after the output of counter reaches a predetermined range.
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申请公布号 |
US2011007859(A1) |
申请公布日期 |
2011.01.13 |
申请号 |
US20100790319 |
申请日期 |
2010.05.28 |
申请人 |
RENESAS ELECTRONICS CORPORATION |
发明人 |
UEDA KEISUKE;UOZUMI TOSHIYA;ENDO RYO |
分类号 |
H03D3/24;H03L7/08 |
主分类号 |
H03D3/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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