发明名称 MULTILAYER WIRING BOARD
摘要 PROBLEM TO BE SOLVED: To provide a multilayer wiring board having a surface wiring layer whose plating defect and no plating are suppressed not through glass etching while maintaining consistency of shrinkage with an insulating base.SOLUTION: The multilayer wiring board has the surface wiring layer 2 composed of a first layer 21 provided on the side of the insulating base 1 and a plurality of plating layers 22 provided on the first layer 21, wherein the first layer 21 contains 95.69 to 96.62 mass% of copper and 3.38 to 4.31 mass% of glass phase, and based on 100 mass% in total of the components contained in the glass phase, the first layer 21 contains 48.0 to 51.0 mass% of Si in terms of SiO, 9.8 to 10.2 mass% of Al in terms of AlO, 0.1 to 0.3 mass% of Mg in terms of MgO, 14.0 to 16.0 mass% of Ca in terms of CaO, 21.0 to 24.0 mass% of Ba in terms of BaO, and 2.4 to 3.0 mass% of Sr in terms of SrO.
申请公布号 JP2011009404(A) 申请公布日期 2011.01.13
申请号 JP20090150682 申请日期 2009.06.25
申请人 KYOCERA CORP 发明人 SAITO SHINTARO
分类号 H05K3/46 主分类号 H05K3/46
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