发明名称 Circuit board with embedded passive component and manufacturing method thereof
摘要 The present disclosure relates to a semiconductor device substrate and a method for making the same. The semiconductor device substrate includes a first dielectric layer, a second dielectric layer and an electronic component. The first dielectric layer includes a body portion, and a wall portion protruded from a first surface of the body portion. The wall portion has an end. The second dielectric layer has a first surface and an opposing second surface. The first surface of the second dielectric layer is adjacent to the first surface of the body portion. The second dielectric layer surrounds the wall portion. The end of the wall portion extends beyond the second surface of the second dielectric layer. The electronic component includes a first electrical contact and a second electrical contact. At least a part of the electronic component is surrounded by the wall portion.
申请公布号 US9426891(B2) 申请公布日期 2016.08.23
申请号 US201414550615 申请日期 2014.11.21
申请人 ADVANCED SEMICONDUCTOR ENGINEERING, INC. 发明人 Tsai Li-Chuan;Lee Chih-Cheng
分类号 H01L23/52;H05K1/18;H01L21/48;H01L23/498;H05K3/34;H05K3/00 主分类号 H01L23/52
代理机构 Foley & Lardner LLP 代理人 Foley & Lardner LLP ;Liu Cliff Z.;Murch Angela D.
主权项 1. A semiconductor device substrate, comprising: a first dielectric layer comprising a body portion and a wall portion protruded from a first surface of the body portion, the wall portion having an end; a second dielectric layer having a first surface and an opposing second surface, the first surface of the second dielectric layer being adjacent to the first surface of the body portion, the second dielectric layer surrounding the wall portion, the end of the wall portion extending beyond the second surface of the second dielectric layer; an electronic component comprising a first electrical contact and a second electrical contact, at least a part of the electronic component being surrounded by the wall portion; a first patterned conductive layer embedded in the second surface of the second dielectric layer; and a second patterned conductive layer disposed on the second surface of the second dielectric layer and an exposed surface of the first patterned conductive layer, wherein the second patterned conductive layer is aligned with the first electrical contact, the second electrical contact and the end of the wall portion.
地址 Kaohsiung TW