High-voltage insulated gate field-effect transistor

摘要

A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source region (14) and a drain region (19), the drain region (19) being formed with an extended well region (17) having one or more buried layers (60) of opposite conduction type sandwiched therein. The one or more buried layers (60) create an associated plurality of parallel JFET conduction channels (41) in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance. A tap region (700) of same conductivity type as that of the drain region is disposed in the well region near a perimeter boundary thereof.