发明名称 Method and mechanism for implementing extraction for an integrated circuit design
摘要 An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction can be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.
申请公布号 US7870517(B1) 申请公布日期 2011.01.11
申请号 US20070741699 申请日期 2007.04.27
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 NEQUIST ERIC;BRASHEARS RICHARD;LIBERTY MATTHEW A.;MCSHERRY MICHAEL C.
分类号 G06F17/50 主分类号 G06F17/50
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