发明名称 |
Methods and apparatus for controlling hierarchical cache memory |
摘要 |
Methods and apparatus for controlling hierarchical cache memories permit controlling a first level cache memory including a plurality of cache lines and controlling a next lower level cache memory including a plurality of cache lines. An additional memory may be associated with the next lower level cache memory and include a plurality of memory lines, the number of memory lines corresponding to the number of cache lines in a way set of the first level cache memory. Alternatively, the memory lines may include L-flags for multiple cache lines of each way set of the next lower level cache memory. L-flags associated with a given index plus any index offset from the first level cache memory may be contained in a single memory line of the additional memory.
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申请公布号 |
US7870340(B2) |
申请公布日期 |
2011.01.11 |
申请号 |
US20080290141 |
申请日期 |
2008.10.28 |
申请人 |
SONY COMPUTER ENTERTAINMENT INC. |
发明人 |
MAGOSHI HIDETAKA |
分类号 |
G06F12/00;G06F12/08;G06F13/00;G06F13/28 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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