发明名称 |
Method of fabricating power semiconductor device |
摘要 |
Wider and narrower trenches are formed in a substrate. A first gate material layer is deposited but not fully fills the wider trench. The first gate material layer in the wider trench and above the substrate original surface is removed by isotropic or anisotropic etching back. A first dopant layer is formed in the surface layer of the substrate at the original surface and the sidewall and bottom of the wider trench by tilt ion implantation. A second gate material layer is deposited to fully fill the trenches. The gate material layer above the original surface is removed by anisotropic etching back. A second dopant layer is formed in the surface layer of the substrate at the original surface by ion implantation. The dopants are driven-in to form a base in the substrate and a bottom-lightly-doped layer surrounding the bottom of the wider trench and adjacent to the base.
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申请公布号 |
US7867854(B2) |
申请公布日期 |
2011.01.11 |
申请号 |
US20090507808 |
申请日期 |
2009.07.23 |
申请人 |
ANPEC ELECTRONICS CORPORATION |
发明人 |
LIN WEI-CHIEH;HSU HSIN-YU;YANG GUO-LIANG;YEH JEN-HAO |
分类号 |
H01L21/336 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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