发明名称 |
Method and apparatus for frequency independent processor utilization recording register in a simultaneously multi-threaded processor |
摘要 |
Mechanism for accurately measuring useful capacity of a processor allocated to each thread in a simultaneously multi-threading data processing system. Instructions dispatched from multiple threads are executed by the processor on a same clock cycle. A determination is made whether Time Base (TB) register bit (60) is changing. A dispatch charge value is determined for each thread, and added to the Processor Utilization Resource Register for each thread when TB bit (60) changes.
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申请公布号 |
US7870406(B2) |
申请公布日期 |
2011.01.11 |
申请号 |
US20050050325 |
申请日期 |
2005.02.03 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ARNDT RICHARD LOUIS;SINHAROY BALARAM;SWANEY SCOTT BARNETT;WARD KENNETH LUNDY |
分类号 |
G06F1/00 |
主分类号 |
G06F1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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