| 摘要 |
PURPOSE: A delay locked loop circuit is provided to stably perform delay locked regardless of the level change of an external power voltage. CONSTITUTION: A voltage level detection unit(280) detects the level of an external power voltage. A phase comparator(200) compares the phase of a feedback clock with the phase of the source clock. A clock delay unit delays a source clock by a start delay unit before a predetermined delay and a connection delay unit after the predetermined delay to output the source clock as a delayed locked clock. A delay duplication model unit(240) outputs a feedback clock by applying the real delay condition of the source clock to the delay lock clock.
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