发明名称 |
Integrated circuit for electronic timepiece and electronic timepiece |
摘要 |
In response to a system reset signal inputted into a system reset port, a control circuit sets a general-purpose port to a high level first. Then, when a mode A is set in an integrated circuit for electronic timepiece, the control circuit sets the general-purpose output port to a low level after an elapse of a first time and when a mode B is set, it sets the general-purpose output port to a low level after an elapse of a second time. In this manner, a mode information signal having a pulse width corresponding to the mode is outputted from the general-purpose output port. It thus becomes possible to reduce the size without adding a special configuration for mode confirmation and to perform a confirmation in a short time.
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申请公布号 |
US2011002197(A1) |
申请公布日期 |
2011.01.06 |
申请号 |
US20100803560 |
申请日期 |
2010.06.29 |
申请人 |
OGASAWARA KENJI;TAKAKURA AKIRA;MANAKA SABURO;SAKUMOTO KAZUMI;SHIMIZU HIROSHI;HONMURA KEISHI;NOGUCHI ERIKO;KATO KAZUO;HASEGAWA TAKANORI;IHASHI TOMOHIRO;YAMAMOTO KOSUKE |
发明人 |
OGASAWARA KENJI;TAKAKURA AKIRA;MANAKA SABURO;SAKUMOTO KAZUMI;SHIMIZU HIROSHI;HONMURA KEISHI;NOGUCHI ERIKO;KATO KAZUO;HASEGAWA TAKANORI;IHASHI TOMOHIRO;YAMAMOTO KOSUKE |
分类号 |
G04C9/00 |
主分类号 |
G04C9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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