发明名称 DIFFERENTIAL RECEPTION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a differential reception circuit provided with a differential pair, which reduces a delay difference of changing timing of rising and falling of data to be outputted.SOLUTION: The differential reception circuit is equipped with: a differential amplifier circuit 1 that is provided with a differential pair and amplifies complementary input signals inp and inn to be input and outputs complementary output signals A and B; a first inverter line that is provided with two or more inverters InvA1, InvA2, InvA3 connected in series in which one signal A of the complementary output signals outputted by the differential amplifier circuit is inputted on first stage; and a second inverter line that is provided with at least one inverter InvB1, InvB2 to which the other signal B of the complementary output signal output by the differential amplifier circuit is inputted, and that is connected in series when two or more inverters are provided, wherein the other of the complementary output signals is inputted on the first stage. The outputs of a set of two inverters having stages different by one in the number of stages from the first stages of the first and second inverter lines are connected.
申请公布号 JP2011004182(A) 申请公布日期 2011.01.06
申请号 JP20090145784 申请日期 2009.06.18
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 MORII MASAHARU;LIU LIANG
分类号 H03K19/0175;H03K5/04;H04L25/02 主分类号 H03K19/0175
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