| 摘要 |
<p>Flip-flop memory cells (1, 2) are connected to a bit line pair (BL, XBL), and are connected to each word line (WL1, WL2). A word line driver (5) outputs a word line selection pulse, during a word line selection period, to one of the word lines (WL1, WL2). A write circuit (3) imparts a potential difference, based on input data (DIN, XDIN), to the bit line pair (BL, XBL) after the start of the word line selection period. In the test mode, the potential difference of the bit line pair (BL, XBL) is reset within the word line selection period, while in the normal mode, the potential difference of the bit line pair (BL, XBL) is reset after the word line selection period.</p> |
