发明名称 Priority circuit for dispatching instructions in a superscalar processor having a shared reservation station and processing method
摘要 <p>A priority circuit (120) is connected to a reservation station (110) and a plurality of arithmetic unit (130, 140)s (130, 140) that processes different operations and dispatches, when it is determined that an executable flag indicating that an instruction can be executed by only a specific arithmetic unit (130, 140) is on, an instruction to an arithmetic unit (130, 140) that is different from the specific arithmetic unit (130, 140) and of which a queue is vacant in accordance with the input performed by an instruction decoder (100) and the reservation station (110).</p>
申请公布号 EP2270652(A1) 申请公布日期 2011.01.05
申请号 EP20100167671 申请日期 2010.06.29
申请人 FUJITSU LIMITED 发明人 FUSEJIMA, ATSUSHI;AKIZUKI, YASUNOBU;YOSHIDA, TOSHIO
分类号 G06F9/38 主分类号 G06F9/38
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