| 摘要 |
<p>A chain of at least two operational blocks, each operational block comprising an arithmetic unit and a carry bypass circuit for propagating a carry signal along the chain of blocks, each arithmetic unit comprising first and second inputs, means for receiving a carry input signal, means for generating a carry output signal and means for generating a bypass signal, the bypass signal being active only if, based on the values input into the first and second inputs, the carry input signal is equal to the carry output signal. Each operational block further comprises receiving means for receiving the bypass signal from the arithmetic unit of a first operational block in the chain and the carry input signal, the carry output signal and the bypass signal from the arithmetic unit of a second operational block in the chain, the second operational block being the operational block preceding the first operational block in the chain; and switching means arranged to propagate the carry output signal of the first operational block if the bypass signal of the first operational block is inactive, propagate the carry output signal of the second operational block if the bypass signal of the first operational block is active and the bypass signal of the second operational block is inactive and propagate the carry input signal of the second operational block if the bypass signal of the first operational block is active and the bypass signal of the second operational block is active.</p> |
