| 摘要 |
To produce a vertical field effect transistor (10), at least one structure (12) is formed on a substrate (13) to form the channel zone using a hard mask (52). An electrical insulation spacer layer (56) is applied close to the substrate, after forming the structure, followed by the application of an electrically conductive or semiconductor gate electrode layer (60) to form the control electrode. The electrode layer surface is smoothed flat with further etching of the flat surface to expose a part of the structure or its insulation cover. |
