发明名称 |
Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells |
摘要 |
Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.
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申请公布号 |
US7864592(B2) |
申请公布日期 |
2011.01.04 |
申请号 |
US20090551936 |
申请日期 |
2009.09.01 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
TAKEUCHI KEN;TANAKA TOMOHARU;SHIBATA NOBORU |
分类号 |
G11C16/04;G11C16/06;G11C7/10;G11C11/56;G11C16/00;G11C16/02;H01L21/8247;H01L27/115;H01L29/788;H01L29/792 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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