发明名称 Efficient switching architecture with reduced stub lengths
摘要 A switching topology for communicating signals in an automatic test system includes a plurality of switching circuits each for selectively passing signals or crossing signals. Switching circuits are connected together such that each node of any switching circuit connects to no more than one node of any other switching circuit. This topology offers improved signal integrity, reduced cost, and reduced space as compared with conventional, matrix-style switching topologies.
申请公布号 US7863888(B2) 申请公布日期 2011.01.04
申请号 US20050191198 申请日期 2005.07.27
申请人 TERADYNE, INC. 发明人 XU FANG
分类号 H03K17/00;G01R1/073;G01R31/319;H04M3/00;H04Q3/545 主分类号 H03K17/00
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