CLOCK GENERATING CIRCUIT AND TEST SYSTEM

摘要

PURPOSE: A clock generation circuit and a test system thereof are provided to be applied to a device having various frequency properties. CONSTITUTION: A controller(210) receives an instruction] from the outside, generates a loop control signal and an oscillating clock signal from a phase locked loop(220). The controller controls the frequency of an oscillation clock signal. The phase locked loop receives a loop control signal and generates the reference clock signal in a specific frequency. A clock bank part(230) receives an oscillation clock signal and generates a plurality of frequency-divided clock signals by dividing the oscillating clock signal based on the oscillation control signal.