发明名称 |
PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES |
摘要 |
A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line.
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申请公布号 |
US2010329058(A1) |
申请公布日期 |
2010.12.30 |
申请号 |
US20100868341 |
申请日期 |
2010.08.25 |
申请人 |
SUTARDJA SEHAT;SU JASON T;CHEN HONG-YI;SHEU JASON;TJENG JENSEN |
发明人 |
SUTARDJA SEHAT;SU JASON T.;CHEN HONG-YI;SHEU JASON;TJENG JENSEN |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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