| 摘要 |
A parallel-to-serial converting circuit includes a first alignment unit configured to receive and serially align parallel data included in a first group selected from a plurality of parallel data and to output serially aligned parallel data. The parallel-to-serial converting circuit also includes a second alignment unit configured to receive and serially align parallel data included in a second group selected from a plurality of parallel data and to output serially aligned parallel data. The parallel-to-serial converting circuit further includes a third alignment unit configured to serially align and output the serially aligned parallel data that is output from the first alignment unit and the second alignment unit. The first alignment unit and the second alignment unit drive an output node in response to activated data of received parallel data.
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