| 摘要 |
The invention concerns a soft output Viterbi algorithm (SOVA) decoder arranged to decode symbols received over a transmission channel, the symbols indicating a state transition between two states of a plurality of states that determines a decoded data value, the SOVA decoder comprising a reliability memory unit (RMU, 800) comprising at least four stages of logic units, each logic unit comprising a single buffer and at least four stages comprising a plurality of full stages (601, 602) comprising a separate logic unit corresponding to each of said plurality of states; and a plurality of compact stages (801) comprising half or less than half the number of logic units than the number of said plurality of states, each logic unit corresponding to two of said plurality of states.
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