| 摘要 |
A flash memory device comprising: a plurality of flash memory cells; and a processor that is configured to perform operations including: receive, at a flash memory device, a request to write data to a plurality of flash memory cells; identify one or more current operational settings associated with the plurality of flash memory cells or the flash memory device; select, by the flash memory device, a write interleaving ratio based on the current operational settings, wherein the write interleaving ratio indicates a number of flash memory cells to be accessed in parallel during a write operation; write the data to the plurality of flash memory cells using the selected write interleaving ratio; receive, at the flash memory device, a request to read data from the plurality of flash memory cells; select, by the flash memory device, a read interleaving ratio based on the current operational settings, wherein the read interleaving ratio indicates a number of the plurality of flash memory cells to be accessed in parallel during a read operation, wherein the selected read interleaving ratio differs from the selected write interleaving ratio; and read the requested data from the plurality of flash memory cell using the selected read interleaving ratio. |
