| 摘要 |
<p>A shift register includes cascade-connected stages, each of which includes a data latch and an output stage. In at least one embodiment, the latch has a single data input which, in use, receives a date signal from a preceding or succeeding stage. The output stage includes a first switch, which passes a clock signal to the stage output when the output stage is activated by the latch. The output stage also comprises a second switch, which passes the lower supply voltage to the stage output when the output stage is inactive.</p> |
