| 摘要 |
<p>There is provided a circuit and method for detecting a bad clock condition on a clock signal, the method comprising: sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal, such that a respective first plurality of samples are produced; determining whether all of the first plurality of samples have a first logic state; sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal, such that a respective second plurality of samples are produced; determining whether all of the second plurality of samples have a second logic state; and determining that the bad clock condition exists on the clock signal if at least one of the following conditions is met: it is determined that all of the first plurality of samples have the first logic state, or it is determined that all of the second plurality of samples have the second logic state.</p> |
