发明名称 Second chance replacement mechanism for a highly associative cache memory of a processor
摘要 A cache memory system includes a cache memory and a block replacement controller. The cache memory may include a plurality of sets, each set including a plurality of block storage locations. The block replacement controller may maintain a separate count value corresponding to each set of the cache memory. The separate count value points to an eligible block storage location within the given set to store replacement data. The block replacement controller may maintain for each of at least some of the block storage locations, an associated recent access bit indicative of whether the corresponding block storage location was recently accessed. In addition, the block replacement controller may store the replacement data within the eligible block storage location pointed to by the separate count value depending upon whether a particular recent access bit indicates that the eligible block storage location was recently accessed.
申请公布号 US7861041(B2) 申请公布日期 2010.12.28
申请号 US20070849515 申请日期 2007.09.04
申请人 ADVANCED MICRO DEVICES, INC. 发明人 WILLIAMS JAMES D
分类号 G06F12/00 主分类号 G06F12/00
代理机构 代理人
主权项
地址