| 摘要 |
A delay means, in response to a delay control signal, performs delay control of the phase of a clock input signal, and outputs it. A selector means, during a speed test, selects a clock input signal from among a clock input signal from a delay unit, and the input signal from an external terminal. A conversion means samples the signal outputted from the selector means based on the sampling clock signal, converts a signal format and outputs it. A clock data recovery means generates a sampling clock signal having a phase depending on the signal inputted to the conversion means, and supplies it to the conversion means. By monitoring the control code for controlling the phase of the sampling clock, a correlation is obtained between a delay variation amount and a code variation amount, and a speed test is performed.
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