发明名称 Providing a set aside mechanism for posted interrupt transactions
摘要 In one embodiment, a method includes receiving an incoming posted transaction in a processor complex from a peripheral device, determining if the transaction is an interrupt transaction, and if so routing it to a first queue, and otherwise routing it to a second queue. Other embodiments are described and claimed.
申请公布号 US7861024(B2) 申请公布日期 2010.12.28
申请号 US20080286324 申请日期 2008.09.30
申请人 INTEL CORPORATION 发明人 WHITE BRYAN R.;MORAN DOUGLAS
分类号 G06F13/00 主分类号 G06F13/00
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