| 摘要 |
A serial communication system includes a master processor and a slave processor. A CS signal for requesting a serial communication is output from the master processor, and an OK_INV signal for responding to the CS signal is output from the slave processor. When a CS signal is an active state, the master processor executes a serial communications of a preset number of bits every time that a level of the OK_INV signal is reversed. The slave processor inverts a level of an OK_INV signal in response to the CS signal shifting to the active state. The slave processor changes the level of the OK_INV signal every time that a serial communication of a preset number of bits is completed.
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