| 摘要 |
PURPOSE: A dynamic domino circuit is provided to prevent the generation of malfunctions by efficiently controlling the phase and the duty ratio of a plurality of internal clock signals. CONSTITUTION: A clock generator(100) generates a plurality of internal clock signals(CK) with pulse signals(P) and phases based on a global clock signal(GCLK). The phases of the internal clock signals are successively delayed. A domino circuit(200) successively performs a plurality of logic operations based on input signals(IN), the pulse signals, and the internal clock signals. The domino circuit generates an output signal(Q) synchronized with the pulse signal.
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