| 摘要 |
PROBLEM TO BE SOLVED: To provide a data aligning circuit of a semiconductor memory device that can be operated speedily. SOLUTION: The data aligning circuit of the semiconductor memory device includes: a first control section for generating a first control signal group according to an address group, a clock, and a latency signal; a second control section for generating a second control signal group according to the address group, the clock, and the latency signal; a first alignment section for aligning a parallel data group to a first serial data group according to the first control signal group; and a second alignment section for aligning the parallel data group to a second serial data group according to the second control signal group. COPYRIGHT: (C)2011,JPO&INPIT |
